By Majid Sarrafzadeh
This article treats the actual layout of very huge scale built-in circuits progressively and systematically. It examines the layout challenge and the layout approach with the purpose of comparing the potency of automated layout platforms via algorithmic research. The structure challenge is seen as a set of sub-problems which might be separately solved successfully after which successfully mixed. Initially,the textual content reports VLSI know-how after which examines format ideas and telephone new release concepts.
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Extra info for An Introduction to VLSI Physical Design
Design a greedy algorithm for finding the maximum number of pairwise disjoint intervals . Design a simulated annealing algorithm for the same problem . Analyze the time complexity of both algorithms . 18. Why is it necessary to redistribute the pins in MCM design? 1 . Given integers m and n and a two-terminal net N represented by terminals (a, b), (c, d) (coordinate (l, 1) represents the northwest corner), and a set of obstacles at coordinates (XI, y I ), (x2, y2) . . (Xk, y k ) ; show an m x n grid graph and a routing interconnecting the terminals of N (or an appropriate "error" message) .
Find an optimal solution to an instance of the two-dimensional bin packing problem (see the previous exercise) assuming : n = 10, A = 6, B = 4, (a 1, bi) = (2, 4), (a2, b2) = (2, 3), (a3, b3) = (1, 2), (aa, b4) = (5, 2), (a5, b5) = (4, 3), (ao, bb) = (3, 3), (a7, b7) = (1, 1), (a8, b8) = (5, 3), (a9, b9) = (2, 4), (alo, b1o) _ (3, 5) . Solve the same problem with A = 5, B = 4 . 15 . Design a greedy algorithm for solving a restricted class of the two-dimensional bin packing problem where A = B and a, = b, for all i .
The process is as follows . 1 . Calculate the ratio gain r(i) for every node i, and set all nodes to be in the unlocked state . 2. Select an unlocked node i with the largest ratio gain from two subsets . 3. Move node i to the other side and lock it . 4. Update the ratio gains for the remaining affected and unlocked nodes . 6 An example of the first two phases . (a) The initialization phase from s to t ; (b) the initialization phase from t to s ; (c) left-iterative shifting ; (d) right-iterative shifting .
An Introduction to VLSI Physical Design by Majid Sarrafzadeh